Moore’s Law and 28nm Yield
This blog is a follow-up to my second most viewed page Moore’s Law and 40nm Yield, with a strong recommendation of how to design for yield at the advanced nodes (32/28/22nm) with Verify High-Sigma design technology.
In today’s highly competitive semiconductor industry, profitability hinges on high yield, competitive design performance, and rapid time to market. For the designer, this translates to the need to manage diverse variations (global and local process variations, environmental variations, etc.), reconcile yield with performance (power, speed, area, etc.), while under intense time pressures. This is an enormous challenge and it is getting even harder as Moore’s Law hits the advanced process nodes.
Case in point: Circuit blocks such as complex standard cells or memory bit cells are repeated thousands or even millions of times on a die. For the overall chip to have good yield, the repeated block must have extremely high yield. Calculating yield in this context is very important due to increasing process variations at each new technology node.
One approach would be to use Monte Carlo sampling. Unfortunately, this would require far too many simulations: a circuit with 99.9999% yield would need, on average, 1 million samples from the true distribution just to observe a single failure against circuit specifications.
Compared to a plain Monte Carlo simulation, Verify High-Sigma design is orders of magnitude faster for estimating yields of high sigma circuits.
With a normal Monte Carlo run, process points are drawn directly from the process variation distribution. The problem, as noted earlier, is that far too many samples are needed in order to get failures in the design. Verify High-Sigma Design changes this by sampling from a different distribution, in which a greater proportion of samples are failures. This approach is a variant of importance sampling. Verify High-Sigma Design estimates the yield of high-sigma circuits by:
- Creating a new sampling distribution such that a greater proportion of samples are failures.
- Drawing samples from the new distribution, simulating them, and seeing if they meet specifications.
- Estimating yield by mathematically unbiasing the samples, according to importance sampling formula.
- Computing yield accuracy, using a statistical technique called bootstrapping.
To illustrate that Verify High-Sigma (VHS) design returns yield estimates as accurate as a standard Monte Carlo (MC) run, the following table compares MC and VHS yield estimation results across 6 different circuits on moderate-yield circuits (moderate yield so that MC only needs a moderate number of samples to make a good yield estimate). For all 6 cases, the yield estimates for VHS and MC agree because their yield confidence bounds overlap.
| Circuit | MC Yield (up to 10K samples) | VHS Yield (250 samples) |
| Current mirror | 99.580% (99.433% – 99.689%) | 99.709% (99.569% – 99.808%) |
| GMC | 99.836% (99.519% – 99.944%) | 99.831% (99.752% – 99.885%) |
| LNA | 99.950% (99.883% – 99.979%) | 99.888% (99.760% – 99.9662%) |
| Folded opamp | 99.221% (98.027% – 99.699%) | 99.490% (98.639% – 99.370%) |
| CP | 99.597% (99.410% – 99.725%) | 99.522% (99.291% – 99.682%) |
When design teams and managers consider which advanced technologies to incorporate in their flows, their metrics include quality of results (QoR), use model, ease of adoption, and cost. Verify High-Sigma design technology addresses each of these metrics. Designers can improve the quality of their results by changing their designs using High-Sigma extracted corners. They can statistically verify their designs with SPICE accuracy in a relatively short amount of time.
I think the idea of “yield” has to change at some point. We can keep making things smaller but at some point you just won’t be able to get 100% of it working on any die (for large chips). The methodology needs to change to something that is fault-tolerant in manufacturing (and use). Large (regular) chips like FPGAs and memories are done that way now, it looks to me like we need tools to do it for more general purpose designs.
Yes, Kevin is right. But even more so is Dan, as we still need assurance that the number of faults/failures in any region is low enough that the chosen fault-tolerating algorithm can cope. Verify high sigma is one way to do this. But it pays to be aware that many of the unbiasing algorithms are still relatively crude, so the accuracy can degrade under some conditions. That said, analogue designers have long used the even cruder method of uniformly bloated distributions without unbiasing.
Another consideration is: how well does RTL design work on high-sigma Silicon?
My view is that in any chain of RTL blocks there will be a “weakest link” that sets the maximum speed of the chain if you clock them together. With high-sigma you will have a higher probability of a particularly slow block, and therefore it’s likely that you will lose a lot of available performance. I suspect a shift to GALS or completely asynchronous design will be required to make best use of Silicon as dimensions shrink.
Advanced sampling and Variance Reduction techniques (e.g. QMC, LHS, Importance Sampling, Adaptive Sampling, and Control Variate) are all very great analysis techniques. They, indeed, have shown promising results in yield estimation of different types of VLSI circuits.
However, I think the more important is the “design” for yield, and how can we benefit from the advanced sampling-based “yield estimation” methods in automatic “yield optimization”?