TSMC Open Innovation Platform Explained
Launched in April 2008, the TSMC Open Innovation Platform initiative is a collaborative strategy aimed at breaking the bottlenecks of semiconductor design enablement in order to promote growth for the industry as a whole. The TSMC iPDK Debate: Lets Play Monopoly! blog I did provides more technical detail.
While Wafer count is climbing, an estimated 20M in 2009 to 30M in 2013, semiconductor design enablement (includes Electronic Design Automation-EDA, Semiconductor Intellectual Property-IP, and Design Services-DS) will continue to stagnate and consolidate.
The main reason for the disjointed wafer count increase and design enablement revenue stalling is FPGAs. As programmable devices advance in speed and density, medium-to-small volume projects and emerging technology companies will continue to leverage the low barrier to entry of FPGAs. Wafer count climbs from FPGA vendors such as Xilinx, Altera, and Actel, while ASIC design starts decline.
Other reasons for the ASIC design start decline include:
- High cost, it takes $50-70M to get an ASIC to market.
- Increased SOC design density and complexity, the chips are bigger so there are less of them and require many more resources to complete.
- High mortality rate, an estimated 50% of the ASIC design starts do not make it into production.
- Less ASIC design starts equals less design experience, less design experience equals higher ASIC mortality rate.
The TSMC Open Innovation Platform promotes timeliness-driven innovation amongst the semiconductor design community, its ecosystem partners and TSMC’s IP, design implementation and DFM capabilities, process technology and backend services. The Open Innovation Platform™ includes a set of ecosystem interfaces and collaborative components initiated and supported by TSMC that efficiently empowers innovation throughout the supply chain and enables the creation and sharing of newly created revenue and profitability. TSMC’s AAA initiative is a critical part of the Open Innovation Platform™, providing the accuracy and quality required by ecosystem interfaces and collaborative components.
The financial goal of OIP is obvious, to reduce waste in the semiconductor design enablement supply chain. People in this industry are accustomed to waste, business as usual, so this is a significant challenge! Jack Harding of eSilicon estimates a 20% waste due to inefficiencies and lack of experience. I say it is closer to 30% if you include the ASIC mortality rate. 20-30% of $50-70M is a significant amount, especially if you are asking a VC for it.
The TSMC OIP targets include the following areas of inefficiencies:
- PDKs, the iPDK standard is innovation driven versus format driven, which reduces foundry and customer support costs.
- EDA Reference Flows and tool qualification, verified design sign-off flows reduce both costs and customer learning curves.
- TSMC IP portal, documenting silicon proven IP from both TSMC and commercial IP vendors such as Virage Logic. Cross distribution deals are also possible.
- TSMC collaborated services, such as Tela Innovations Power and Area Trim.
The bottom line is that to increase ASIC design starts we must decrease the barrier to entry, we must reduce risk, we must all focus on success based business models:
- TSMC is certainly success based with wafer pricing but must look at reducing NRE (mask costs) which are in the millions of dollars.
- IP companies are success based capable with foundry sponsored IP (free to customers), and royalty based IP, but there are still significant up-front licensing fees for leading edge products.
- Design Services (eSilicon) are definitely success based with per chip pricing for working silicon.
- EDA is still in the dark ages with yearly subscriptions or all-you-can eat product dump pricing where you pay whether you use it or not, whether you are successful or not.
This was the second OIP conference, it was stocked with executives from TSMC and the design enablement food chain. The keynotes, panels, and discussions were highly interactive, the format and content is exactly what our industry needs to scale and move forward in a profitable manner.
Dan,
If interested parties had a way to mitigate their design investment (similar to how other industries use futures to lock in costs & asps), do you think there would be a viable market for such instruments?
Brian Piercy
Brian,
I would say “yes”. As IP reuse grows I think anyone prepared to back their IP with a guarantee will win a greater market share. However, most small IP vendors cannot afford the cost of someone respinning their SoC, so those businesses need to be able to buy insurance from third parties. You then run into the problem of how to qualify a piece of IP that has not been used before, and I would say that’s a problem with the current crop of EDA tools not being up to the job.
Kev.
Let’s say you’re an IDM (or a fabless outfit). You’re taping out in 3 months, on a new tech node, with a couple of new 3rd party IPs. 1000 wafers needed for the product’s life, at 80% avg yield. Let’s say the node is 40nm LP logic with a 300mm wfr price at $2500 each. (I’m guessing.)
You look around & realize you’ve got a potential 20% yield loss risk on your hands. If your finance guy could hedge the risk with a derivative at the right ’strike price’, would you go for it?
Brian, Please explain the whole process. As you have stated, I think if all the information is already known, who is going to provide the hedge? What is in it for the company providing the hedge?
Anand, one important point: the information in my example may be known as market intelligence except for the fears of a yield bust – which is project-specific & almost always proprietary to that customer. So the marketplace is dealing with less-than-perfect information, which is the basis for this idea.
The buyer in my example wants to BUY the RIGHT TO PURCHASE those wafers for, say, Q2′10 deliveries. The market price is $2500, but the 20% yield crash effectively make the buyer’s price closer to $3000. So the buyer wishes to BUY a 40nm wafer futures contract at a $2500 strike price to hedge his costs. This proposed transaction is in addition to the contract wafer price agreed upon by the IDM/design house and their foundry partner.
The customer(s) providing the hedge are SELLING the right to purchase the same derivative. The seller probably has different, but recognizable, motivations. (Perhaps the seller heard of a possible 40nm yield bust due to flaky IPs, and wants to take advantage of the situation.)
It’s important to note that this is not a scheme for one firm to sell semiconductor yield insurance. An online market would find the economically best match of buyers & sellers, recommend an optimum price for the derivative, and conduct the transaction.
I truly welcome any rocks, spears & caveats. It seems to me that our industry is overdue for something like this. If the assumptions are correct.
Brian, I don’t understand your proposal at all. Stating your example, an IDM or design house has secured wafer purchases for $2500. The buyer assumes 100 GDPW and so expected die cost is $25. “Yield bust” occurs, however, and there is only 83 GDPW raising actual die cost to $30. So far, I think, I’ve re-stated the problem you pose(?) If this is the problem, though, then securing more wafers at $2500 doesn’t help. The additional wafers still may have the yield problem, so die cost remains higher than plan and the fact is that you don’t know you need the “extra” wafers until yield is (after the fact) measured. The “real” problem in these cases is that you need 17 more die to fulfill market demand and you have to go back to the fab and “expedite” wafers, raising cost further. A “derivative” market that could be useful in this case is a market for “hot lot” slots. Homey (i.e. TSMC), however, don’t play that.
Dan,
Great post, speaks to the core issue in the semi industry. I differ slightly with attributing the cause of ASIC design start decline to FPGAs, however. I think you capture the causes for ASIC design starts appropriately in the list (NRE and risk). FPGA design starts, on the other hand, are in the 80,000 to 90,000 range per year and have been there for a decade. The vast majority of those design starts address market segments where ASICs have generally been inappropriate (system prototyping, small volume apps and board logic consolidation). I think what’s more surprizing is that FPGAs are not taking on the volume applications and growing their revenue more quickly. I comment on this here http://mattrhodes.net/wordpress/?p=129
Matt,
You’re correct – to a point. The derivative idea isn’t meant to attack a supply/demand imbalance. (I can start a 2nd rant on the believability of semi forecasts 3 months before tapeout, but that’s another day.)
The derivative idea is meant to address the FINANCIAL risk inherent in a project forecast. We’re all familiar with them:
Consumer side:
* yield issues, diesize misses, tapeout delays (esp if capacity is secured with %non-refundables), unforeseen NREs, …
Supplier side:
* technology mixes (40nm pushouts, backfilled by 65nm or 90nm starts @ lower ASPs), process yields on newer nodes, throughput/capacity backfires…
All of these boil down to problems of cost or asp per unit area – no different than a farmer’s (or Archer Daniel Midland’s) heartburn over his/her acre of corn.
I’m definitely not interested in a hot lot auction. You’re right, Homey wouldn’t like that.
Keep those cards & letters coming. I’m sure there’s something to this.
Hi: I don’t think you are being fair to EDA. For advanced nodes, the EDA guys are doing a lot of investment by working with foundries well in advance of any tool deployment, and thus EDA is funding the technology node NRE, and since it is bleeding edge the overhead is large. The overheads are even larger due to restrictions on design rule access and testcase distribution imposed by the foundry. I think EDA would gladly accept a shared risk/reward model, its just that any chip company balks at any mention of royalty. They want to be in the best position to maximize profit upside on a winning design. So how would you propose EDA get compensated for their investment ?