Daniel Nenni

To follow up one of my most viewed blogs: TSMC 40nm Yield Explained, let’s talk about Restrictive Design Rules (RDRs) and 32/28nm yield. RDRs have been seriously discussed since 65nm, by restricting the freedom layout designers enjoy today a foundry can better guarantee the manufacturability of a semiconductor design. RDRs even have a Wikipedia page.

The #46DAC Advanced Node Panel: Making the Case for Restricted Design Rules was stacked with semiconductor experience: Norma Rodriguez, senior member of technical staff at AMD, Tom Quan, senior director of EDA and design service marketing at TSMC, and Arjun Rajagopal, member of technical staff at TI’s DSP group.

Digital 32/28nm designs are less complicated. According to Tom Quan, design and modeling infrastructure for 32/28 nm is ready at TSMC, it includes statistical Spice models, a reference flow, and RDR-based standard cells with regular layout patterns. Arjun Rajagopal admitted that RDRs will increase area, but will help with process variability and predictability. Norma Rodriguez spoke in detail about 22nm RDRs but my feeling is that it was AMD microprocessor centric, which is quite different than GP or LP foundry processes.

I agree with Tom Quan, digital designs will be less of a problem with RDRs, but analog and mixed signal designs are another challenge all together. At 45nm and below, proximity variation effects (channel stress, contact spacing, poly-to-poly spacing, STI spacing,  well spacing, and OD-to-OD spacing) are a major disturbance.

It’s a catch-22 really, you don’t know the actual effects until layout, but will have to iterate back to the schematic to adjust for them, creating a time consuming iterative loop. The unfortunate reality is that probably only 10% of the instances in an analog mixed/signal design will have proximity problems so guard banding 100% of the devices will be costly.

Let’s talk about the analog design flow to highlight how these proximity effects could fundamentally alter a circuit designers job. In my experience, the designer creates a schematic and uses foundry-provided spice models to run simulations to determine performance under nominal process conditions. At 32/28nm, the designer is aware that various proximity and stress effects will significantly impact circuit behavior. What does this do to the rest of the design flow? The designer needs to simulate over various process/environmental corners, simulate for local mismatch issues to determine yield robustness. All these tasks are typically done during the circuit design stage. But now, with all these proximity effects, should the designer hold off until after layout? Does the designer just assume that the layout engineer will be ultra-conservative using RDR’s (if available), heuristics, or guess-work to guard-band during layout? How about giving the designer visibility/inputs into the layout stage? If the designer could determine which devices are more or less sensitive to proximity effects and be able to provide this information to the layout engineer, it would significantly decrease yield risk during the front end design task at 45nm and below nodes.

The only functional proximity solver that I’m aware of today is from Solido Design. I have been helping Solido with Strategic Foundry Relationships so I know this by experience. For more information, read what Ron Wilson from EDN had to say: Solido adds well-proximity estimation to Variation Designer, or check out the Solido Proximity Package Data Sheet. Proximity variation effects are a serious problem for analog and mixed signal designs at 32/28nm, believe it.