Semiconductor Design and Manufacture Predictability
Predictability is the key to many business success stories. The McDonalds franchise recipe, you always know what you are going to get when you go to a McDonalds, right? Wall Street thrives on predictability, no matter what your reported numbers are, as long as they fit through the advisory goal posts your stock will thrive. Predictability is an even more important part of semiconductor design and manufacture since variables and dependencies increase dramatically throughout the cycle.
Predictability is the driver for the TSMC reference flows and iPDKs, where different tools are tested and certified for predictability. The only predictable semiconductor IP is silicon-proven IP, which is why TSMC has early development partnerships for the top semiconductor IP providers. Using reference flows and silicon-proven IP are excellent ways to improve the predictability of the chip development process, the problem is, most of these efforts focus on detailed implementation tools (like synthesis, P&R, verification, DFM), which means the leverage can be low because the focus is late in the design process. Fixing problems late, during implementation, leads to iterative loops and constrained choices, which rarely gets you where you really want to be. At the #46DAC it was very interesting to see so many implementation point tools promising cures for various design closure diseases due to the lack of predictability, meaning this is a real problem designing at 65nm and below.
As mentioned in Blogging from San Francisco: Beware of Bloggers, I was quite impressed by the BlogFest sponsored by Atrenta, an executive briefing for bloggers. Atrenta offered up CTO Bernard Murphy, VP Strategic Development Mike Fazeli, EDA Visionary Jim Hogan, and VP of Marketing Mike Gianfagnia, for questions and comments in an open format. The combined semiconductor experience of these guys is a staggering 100+ years. Even more impressive, Mike Fazeli’s LinkedIn profile shows 27 years with Texas Instruments in various semiconductor design enablement roles. Here is what Atrenta does:
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start!
At a conceptual level, everyone agrees that doing a better job planning a complex project *before* implementation begins has tangible benefits. What-if loops are shorter, the ability to try different architectures is much greater, and the chance of getting through that expensive implementation flow without overruns is better. We all know it’s easier to move a wall on the drafting table than on the construction site. So you need to know, before implementation, that you will hit your performance target, with a chip that fits in the package, that didn’t exceed the power budget, and could be tested for reasonable cost. The next question is: When will RTL level design tools become part of the foundry reference flows? Soon we all hope.
Daniel, asking “When will RTL level design tools become part of the foundry reference flows?”, there have been papers published at the annual IP Conference in Grenoble, France (formerly IP-SOC) by NXP outlining their own standardized RTL flow centered on their NxBuilder tool (built atop Mentor’s Platform Express, btw). NxBuilder covered their implementation flow from RTL (including IP reuse supported by IP-XACT) through hand-off to back-end, with verification and synthesis along the way. At least for the foundry arrangements that NXP has in place, it has worked for them.
For the likes of TSMC or Global Foundries et al., their perspective is viewed from the opposite end of the funnel and a wide variety of RTL flows could fit. It would be harder to standardize the RTL flow since every company has staked their success on their own preferred methodology (and that funnel gets wider as you go up in levels of abstraction, toward ESL, providing even more options to develop some or all of the RTL, new or pre-existing). Trying to control the target at the entry point to the foundry, as TSMC is doing with iPDK, at least allows them to control what they can control (as you have pointed out, thanks!).
“When will RTL level design tools become part of the foundry reference flows?” – my answer would be: when the foundry owns the RTL and back-end tools. Or alternatively when everyone moves to using the same tools. If I were TSMC and I wanted to simplify things I might be tempted to buy an EDA company and open-source the tools or license them for next to nothing. The FPGA vendors do the latter because they make their money on Silicon sales (as does TSMC).
If, as you suggest, TSMC were to buy an EDA company (Magma?) and open-source the tools, they would in effect be killing the EDA industry (as we know it) altogether and assuming the burden of ensuring that all subsequent generations of silicon were supported. Not that that’s necessarily a bad thing, but it could only happen if TSMC could afford to support the equivalent of the entire EDA industry’s development budget. That might be possible under an open-source model, but I wonder where all subsequent innovation would come from? Lots of little startups operating on an open-source model? An interesting thought, anyway.
Dan,
Improving predictibility (without sandbagging!) is the direct result of three inter-twined strategies:
1. Honestly evaluate and understand past performance on similiar past projects. (Did you ever notice that despite great intentions to anticipate any and all issues, “something” always goes unexpected and causes delay?)
2. Scope the next project consistently with the complexity of past projects. This is tougher than it sounds. Don’t fall into the trap believing that the second time you do something (such as IP reuse) the effort will be trivial.
3. Do a risk analysis for your proposed schedule. This will include any underlying assumptions like productivity, team size or resource availability to name a few. Know when you are being aggressive, because aggressive schedules are by their very nature less predictable!
Do this all well in an economic recession, including tight resources and intense market window pressure and you’ll be a superstar!