Daniel Nenni

www.failblog.org has got to be one of the most entertaining blogs on the internet, hands down. There are daily pictures and videos highlighting human folly and just how idiotic people can be in their everyday lives. The marketing fail pictures are the absolute best, laugh out loud funny!

Speaking of marketing fails, for someone that keeps complaining about EDA marketing FUD, how is Rajeev Madhavan calling analog design a “black art” not FUD? Maybe I’m being too literal here but to me a black art involves magic, voodoo, mysterious stuff. What a thoughtless label for a highly skilled trade bounded by the laws of physics, insulting really, unless of course you are trying to sell something. Rajeev is still one of the best EDA salesman, don’t ever forget it.

Process Variation could be considered a mysterious part of analog design I guess, but it is hardly a black art. TSMC spoke out about process variation in a rare interview with Ron Wilson, EDN Executive Editor and Dr. Jack Sun, TSMC Vice President of R&D: http://www.edn.com/article/CA6569193.html

“The primary problem today, as we take 40 nm into production, is variability,” he says. “There is only so much the process engineers can do to reduce process-based variations in critical quantities. We can characterize the variations, and, in fact, we have very good models today. But they are time-consuming models to use. So, most of our customers still don’t use statistical-design techniques. That means, unavoidably, that we must leave some performance on the table.”

Translation: The big 3 EDA vendors lack the innovative tools to efficiently handle TSMC’s advanced TMI models? Emerging tool companies on the other hand do have innovative products to help prevent design loss caused by process variation. In fact, expect a flood of process variation tool announcements at this years DAC ala the DFM craze of 2004.

In the absence of statistical tools, TSMC must also work to develop process corners that accurately reflect the vastly more complex patterns of variations happening across wafer lots. “We try to find ways to lump parameters together to simplify the corners,” Sun says.

You have (3) options here: Either you do brazzilions of monte carlo simulations wasting engineering resources, use the generic digital process corners provided by the foundry, or you can use a process variation analysis tool to determine the True Corners of the design. Digital corners are not representative of the actual variation and Monte Carlo is painful except as a final verification step. What is needed are more precise corners that represent the manufacturing, environmental, and operating variance that a design is subjected to and are small enough in number so that they can be iterated with rapidly during the circuit design stage. This approach will make it possible to improve performance/yield, reduce power/area/design time, and avoid design failures using today’s nanometer processes.

“But there are, for instance, layout-dependent stress effects. It’s a pain you have to live with. The best we can do is to provide accurate Spice models and restrictive design rules (RDRs) that will reduce the variations.”

This will require a proximity solver, not an easy thing to do. RDRs can guard band a design into production but can leave significant die area on the table, which will alter the risk versus reward equation of a smaller process node. Look for at least one design proximity solver to be announced at DAC. Until then designers will have to iterate between schematic and layout until they get it right.

“Early adopters—companies like Qualcomm and Altera, which are already on 40 nm—have very early and deep collaboration with the process team,” Sun says. “As the process matures, we see a second wave of design teams. These teams still require collaboration, maybe for specific customized features, but otherwise they are working with a proven process and far less uncertainty.”

This spells opportunity for emerging EDA companies, to act as facilitators between the top tier semiconductor companies and the foundries. First step is to get the foundries to use your products, which is an important weed-out process. Seriously, if the foundry does not have confidence in a process variance analysis tool, why would their top tier customers?