TSMC Open Innovation Platform Explained
Launched in April 2008, the TSMC Open Innovation Platform initiative is a collaborative strategy aimed at breaking the bottlenecks of semiconductor design enablement in order to promote growth for the industry as a whole. The TSMC iPDK Debate: Lets Play Monopoly! blog I did provides more technical detail.
While Wafer count is climbing, an estimated 20M in 2009 to 30M in 2013, semiconductor design enablement (includes Electronic Design Automation-EDA, Semiconductor Intellectual Property-IP, and Design Services-DS) will continue to stagnate and consolidate.

The main reason for the disjointed wafer count increase and design enablement revenue stalling is FPGAs. As programmable devices advance in speed and density, medium-to-small volume projects and emerging technology companies will continue to leverage the low barrier to entry of FPGAs. Wafer count climbs from FPGA vendors such as Xilinx, Altera, and Actel, while ASIC design starts decline.
Other reasons for the ASIC design start decline include:
- High cost, it takes $50-70M to get an ASIC to market.
- Increased SOC design density and complexity, the chips are bigger so there are less of them and require many more resources to complete.
- High mortality rate, an estimated 50% of the ASIC design starts do not make it into production.
- Less ASIC design starts equals less design experience, less design experience equals higher ASIC mortality rate.
The TSMC Open Innovation Platform promotes timeliness-driven innovation amongst the semiconductor design community, its ecosystem partners and TSMC’s IP, design implementation and DFM capabilities, process technology and backend services. The Open Innovation Platform™ includes a set of ecosystem interfaces and collaborative components initiated and supported by TSMC that efficiently empowers innovation throughout the supply chain and enables the creation and sharing of newly created revenue and profitability. TSMC’s AAA initiative is a critical part of the Open Innovation Platform™, providing the accuracy and quality required by ecosystem interfaces and collaborative components.
The financial goal of OIP is obvious, to reduce waste in the semiconductor design enablement supply chain. People in this industry are accustomed to waste, business as usual, so this is a significant challenge! Jack Harding of eSilicon estimates a 20% waste due to inefficiencies and lack of experience. I say it is closer to 30% if you include the ASIC mortality rate. 20-30% of $50-70M is a significant amount, especially if you are asking a VC for it.
The TSMC OIP targets include the following areas of inefficiencies:
- PDKs, the iPDK standard is innovation driven versus format driven, which reduces foundry and customer support costs.
- EDA Reference Flows and tool qualification, verified design sign-off flows reduce both costs and customer learning curves.
- TSMC IP portal, documenting silicon proven IP from both TSMC and commercial IP vendors such as Virage Logic. Cross distribution deals are also possible.
- TSMC collaborated services, such as Tela Innovations Power and Area Trim.
The bottom line is that to increase ASIC design starts we must decrease the barrier to entry, we must reduce risk, we must all focus on success based business models:
- TSMC is certainly success based with wafer pricing but must look at reducing NRE (mask costs) which are in the millions of dollars.
- IP companies are success based capable with foundry sponsored IP (free to customers), and royalty based IP, but there are still significant up-front licensing fees for leading edge products.
- Design Services (eSilicon) are definitely success based with per chip pricing for working silicon.
- EDA is still in the dark ages with yearly subscriptions or all-you-can eat product dump pricing where you pay whether you use it or not, whether you are successful or not.
This was the second OIP conference, it was stocked with executives from TSMC and the design enablement food chain. The keynotes, panels, and discussions were highly interactive, the format and content is exactly what our industry needs to scale and move forward in a profitable manner.
Blogging from Hsinchu: ICCAD and 40nm Process Variation
The International Conference on Computer-Aided Design (ICCAD) has always been my favorite semiconductor design enablement event, the signal-to-noise ratio is the highest in the industry! This year ICCAD is November 2-5th at the Double Tree Hotel in San Jose. ICCAD and I are both celebrating our 25th year serving the semiconductor industry.
Welcome to the 2009 International Conference on Computer-Aided Design (ICCAD), ICCAD continues to be the premier — and most selective — conference devoted to technical innovations in design automation. ICCAD’s program of technical papers, tutorials, keynotes and Monday night panel highlights the most important current and future research challenges. A day of colocated workshops on hot topics promises non-stop technical excitement. And as always, a large number of side meetings and social events provide plenty of opportunities for networking and meeting colleagues and friends. Hamid Pirahesh, IBM Fellow at the Almaden Research Center, will deliver the keynote outlining the role of Cloud Computing and key related challenges which represent opportunities for the ICCAD community.
- 438 worldwide submissions and the technical program committee
- 115 excellent papers for presentation
- 31 sessions over the three days of the technical program.
- 3 special sessions focused on providing additional broad perspectives for our CAD audience.
Other than the keynote, the 2 sessions that most interest me are:
(1) The Future of EDA–A conversation with Jim Hogan and Paul McLellan on what EDA needs to change for 2020 success Monday, November 2, 3:00 - 4:00 p.m. | The Silicon Valley Room.
Knowing both Jim and Paul, expect an entertaining discussion on why EDA sucks.
(2) COLOCATED WORKSHOP: Variability Modeling and Characterization , Thursday, November 05, 8:00am – 5:00pm | Siskiyou
Having spent the week in Taiwan getting schooled on foundry Process Corners versus Design Specific Corners, I’m eager to learn anything and everything about variability and modeling I possibly can. Check out my blogs TSMC 40nm Yield Explained and TSMC Process Variation for additional experiences.

Hsinchu Science and Industrial Park is the Silicon Valley of Taiwan with 300+ semiconductor companies. Also called the Windy City, like Chicago, with winds off the China Sea, monsoons, typhoons, and earthquakes, oh my! This week the winds were 20-30mph which was entertaining to say the least. November-December is a real nice time to be here, warm but not too humid. Hsinchu City has an interesting Wikipidia page, lots of history here.

And yes, I flew the dreaded China Air again ( SFO->TPE round trip for $600), but this is really the last time, really! When the plane lands in Taipei and the seat belt lights go off there is an absolute rugby scrum to get off the plane first. I was on an aisle this time so I stood up and was taken out by a woman twice my age and trampled by another twice my size. Of course the plane door wasn’t even open yet so the scrummers were barely in front of me after the dust settled. Then there was the 20 minute wait for immigration and luggage, which makes no sense to me whatsoever. What’s the hurry? To prevent further deplaning injuries I changed my return seat to my usual window so I can watch the scrum from the sidelines.
Next up: A day with the incredible TSMC Design Ecosystem, should be blog worthy for sure.
Semiconductor IP Companies on the move: Virage’s Next eXPerience
In yet another accretive move, Virage Logic will take control of NXP’s CMOS IP business in exchange for 2.5M shares of VIRL stock, NXP will also pay Virage $60M over a 4 year period for IP and design services. The blogs I have seen on this transaction seem negative, or at a minimum confused. Same goes for the Virage ARC acquisition, which is official now, the ARC guys have already started the move to Fremont, CA.
So let me explain something to you ARMchair quarterbacks about selling semiconductor IP, it is one of the most difficult processes you will ever experience. A design-win sale is highly technical, extremely complicated, a real pressure cooker, which explains why the turnover rate for IP sales people is abnormally high. Buying IP is no picnic either, dealing with literally dozens of over-motivated sales professionals who are forcefully hydrated by the corporate fire hose. Reducing the number of IP companies you have to deal with mitigates your design risk, so do not underestimate Virage Logic’s strategy to provide a deep semiconductor IP portfolio, supported by a dedicated sales and support team.
My Blogs on the Semiconductor IP Peloton and Virage’s ARC acquisition explain everything. The bigger question I have is NXP’s strategy, what are they really up to?
Based on the VLSI Technology acquisition in 1999, Philips had a strong position in the semiconductor industry and ranked in the top 20 semiconductor sales leaders. NXP (for Next eXPerience) Semiconductors was spun out by Philips in 2006 with 80% control sold to private equity investors. The transaction put a value of NXP at approximately EUR $8.3 billion. A brilliant move by Phillips of course, realizing that NXP is just another dinosaur in the semiconductor IDM tar pit.
Last December there was a very European changing of the CEO’s, with the NXP CEO Frans van Houten being replaced by semiconductor veteran Richard L. Clemmer. After 4 years of trying to resuscitate the vertical IDM business, the restructuring (asset reduction) started with the sale of the NXP wireless business to STMicro, next the Digital TV / Set-Top Box Business went to Trident systems, and now the CMOS IP business goes to Virage Logic. The NXP business focus is now on high-performance mixed-signal circuits, Richard Clemmer claims that this market is driven by ‘automotive, identity and security, power, lighting and basestations’, which is, in NXP’s analysis, a US $85 billion market.

David Manners’ Blog on the subject suggests that the US $85 billion number is a wet dream to appease the bosses, the private equity firms that have invested billions of dollars in NXP. I agree, definitely a CEO Hail Mary pass.
Paul McLellan’s Blog on the subject suggests that Dutch food sets a low bar, so if you are ever in Eindhoven make sure to try the Indonesian food. I agree 100%! Last time there I tried to eat some deep-fried, ball-shaped, mushy meat-like stuff and almost died. The Dutch cheeses and chocolates are excellent however!
Ron Wilson’s Blog on the subject suggests there may be a darker interpretation: NXP as a heavily-indebted, private-equity-owned company, shut off from short-term credit markets and struggling to service debts. Ron has never been one to perume a pig.
UMC versus GLOBALFOUNDRIES
TSMC Versus Global Foundries and TSMC versus SMIC clearly indicate that TSMC is the number one foundry in the world and it will be that way for the foreseeable future. The question now is who will be number two? Who will seriously challenge TSMC?
UMC has 10 fabs, 8 in Taiwan, 1 in Japan, and 1 in Singapore. Global Foundries will have Chartered’s 6 fabs in Singapore, AMD’s fab in Dresden with 1 more fab under construction in Dresden and another under construction in upstate New York, so 9 fabs in total. UMC just made a key fab acquisition in China (He Jian Technology Co. Ltd.) which has an interesting story to it.
The Chinese semiconductor total addressable market (TAM) is a staggering 1.33B+ people with a median age of 34 years. Fueled by the internet, consumerism is running rampant in China, Western culture is flooding in, allowing the Chinese people to make technology leaps and bounds like no others. Unfortunately, the Chinese government funded semiconductor manufacturing initiatives are struggling due to some serious miscalculations: underestimating the cost and experience required to be successful, underestimating the demand curve of the Chinese consumer, underestimating rapid technological advances, and what it takes to be a competitive semiconductor manufacturer.

Fortunately the political tensions between Taiwan and China are easing, so technology has begun to flow freely between the two countries. The Political Status of Taiwan Wikipedia page is very detailed in case you are interested. If not, here it is in a nutshell, recent Taiwan elections tossed out the DPP (Democratic Progressive Party) and brought in a pro China political party KMT (Chinese Nationalist Party). Also tossed out are the strict Taiwanese laws designed to prevent flight of technology to mainland China, which the DPP controlled Taiwan viewed as a potential military enemy.
This brings us to the UMC acquisition of the Chinese foundry He Jian Technology Co. Ltd. UMC paid $285m for the 85% it did not already own, which had full new KMT Taiwan government approval. Unfortunately the previous 15% UMC purchased did NOT have DPP Taiwan government approval which resulted in the resignation of UMC executives. On January 9th 2006, just hours before being indicted in Taiwan for allegedly making illegal investments in He Jian, UMC chairman Robert Tsao and vice chairman John Hsuan resigned their posts. If convicted, the executives may face jail time of between six months and five years, which is highly unlikely under the new Taiwan KMT government.

TSMC already has manufacturing in China, UMC now has manufacturing in China. TSMC and UMC are both process independent, meaning that they own all of their process technologies outright. SMIC is the largest foundry in China but does not own the process technologies, earlier versions were derivatives of TSMC processes, newer versions will be licensed from IBM. Global Foundries and Chartered Semiconductor do not have China based manufacturing (yet) and also license newer process technologies from IBM.
If you believe, like I do, that manufacturing process technology differentiation is key to semiconductor foundry success. If you believe, as most people do, that the emerging Chinese consumer electronics market is key to semiconductor industry growth, UMC will continue to be a strong #2 contender. Otherwise competitive pricing will rule, generic semiconductor manufacturing processes will dominate, and the foundry consolidation cycle will repeat itself indefinitely.
Blogging From Taiwan: TSMC and Typhoon Parma
According to my lovely wife, natural disasters follow me around when I travel. Out of the hundreds of trips I have made, only a handful involved natural disasters but those are the ones she remembers, most recently: Blogging from Taiwan: Earthquake! Typhoons are the most memorable for me due to the sheer force of nature. Also memorable are the meetings I had at TSMC during typhoons and watching the destruction from atop the Hotel Royal in Hsinchu. Yes TSMC employees work long hours, even when the entire country shuts down for a typhoon, nothing can stop TSMC.

August 2, 2009, Typhoon Morakot was the deadliest typhoon to impact Taiwan in recorded history. It wrought catastrophic damage in Taiwan, leaving 461 people dead and 192 others missing, most of whom are feared dead and roughly $4 billion in damages. The storm produced amazing amounts of rainfall, peaking at 109.3 inches, surpassing the previous record of 68.35 inches set by Typhoon Herb in 1996.
The massive amount of rain triggered enormous mudslides and severe flooding throughout southern Taiwan. One mudslide buried an entire town, killing an estimated 500 people. The slow moving storm also caused widespread damage in China, leaving eight people dead and causing $1.4B in damages. Nearly 2,000 homes were destroyed in the country and 136,000 more were reported to have sustained damage. The storm also caused severe flooding in the northern Philippines that killed 26 people.

Taiwan’s premier Liu Chao-shiuan resigned over the shame of the government’s slow response to Typhoon Morakot. His Cabinet also was resigning en masse, according to Google, which explains the extra warnings and preparations for Typhoon Parma.
According to Taiwan’s Central Weather Bureau website, Parma has winds gusting up to 100 miles per hour, offshore of Taiwan’s southern tip, and was heading north-north west “at a slow rate”. A sea warning for most of Taiwan, issued on Oct. 3, remains in place. Heavy rain is expected in the affected areas.
A magnitude-6.3 earthquake also struck Taiwan on Sunday, hitting at a depth of 15.3 kilometers about 36 kilometers east of Taiwan, the bureau said. No damage or injuries were reported. Nearly a dozen aftershocks have hit in the last 24 hours ranging from 3.6 to 4.7, living on an island paradise does have its drawbacks.
In the wake of natural and unnatural (economic) disasters, TSMC continues to invest, TSMC continues to dominate the semiconductor foundry market segment. With $7.5 billion in net cash and less than $140 million in long-term debt, expect a TSMC announcement this month that will double capital expenditures and increase head count in the 20-30% range for research and development and advanced design methodologies. As for third quarter revenues, expect a near perfect V economic recovery with two of the largest quarterly growth rates following two of the largest quarterly reductions.

The biggest disaster this trip was flying on China Airlines again. Turbulence plagued the flight with neck wrenching force and the noises coming from the fuselage made me wish I had stayed home. Luckily I did not eat the food this time so my intestines survived. Mark my words, I will NEVER EVER fly China Airlines again, believe it.
Blogging from Taiwan: TSMC versus SMIC
This blog is about the legal battle between TSMC and SMIC which is currently playing in the California court system. Taiwan Semiconductor Manufacturing Corporation (TSMC) and Semiconductor Manufacturing International Corporation (SMIC) do what their names suggest – the manufacturing of semiconductors for an international roster of clients. TSMC touts itself as the first chip foundry, SMIC touts itself as the first China-based chip foundry. TSMC is ranked #1 , SMIC is #4, see my blog TSMC vs Global Foundries for more details on capacity and revenues.

The starting point is illustrated above, where SMIC went from equipment being installed in August of 2001, to qualified production in December 2001. As a point of proof, TSMC referred to the Fab of the Year Award that SMIC received from Semiconductor International in 2003, highlighting the fact that just four months after installing equipment in its fab, SMIC had four processes up and running, manufacturing 18 different products. Adding to that suspicion was the claim that SMIC hired away 100+ TSMC employees that had access to the sensitive process data required to bring a fab to production. To begin the legal discovery process, TSMC analyzed SMIC .18m silicon from a Broadcom product and documented stark similarities to the identical product silicon from TSMC. With discovery came incriminating emails which are a centerpiece of the case.

December 2003, TSMC filed suit alleging systematic intellectual-property (IP) theft and patent infringement by SMIC. Witness testimony indicated:
- An estimated 90% of SMIC’s 180nm logic process was copied from TSMC
- SMIC attempted to disguise the origin of the information by internally referring to TSMC and its technology by the code name ‘BKM1′, referring to ‘Best Known Method 1
- SMIC’s use of TSMC technologies was ‘no secret’ and was openly discussed by SMIC engineers
Email supporting this testimony included exchanges between SMIC COO Marco Mora (a fromer TSMC employee) and then TSMC employee, Katy Liu, asking that she transfer TSMC’s process recipe documents and technical training manuals to SMIC. Proving once again, even very smart people can do very stupid things.

Not surprisingly, SMIC agreed to settle the case in February of 2005. Under terms of the settlement, SMIC is to pay TSMC $175 million over 6 years and the companies have agreed to cross license 180nm patent portfolios through December 2010.
In August 2006 TSMC filed a new lawsuit for more than $130 million alleging breach of the 2005 agreement. TSMC claims: SMIC continued copying TSMC manufacturing technology for newer (130nm) manufacturing processes in SMIC’s fabs, it also developed the advanced 90nm process using TSMC’s know-how.
“SMIC has carried out massive corporate espionage directed by certain [of] SMIC’s top operating officers,” the 31-page complaint said. “SMIC lavishly copied the information it stole from TSMC, word for word, line for line, diagram for diagram, and even typographical error for typographical error.”

In November 2006 the High Court in Beijing accepted SMIC’s filing in which it claimed TSMC had intentionally disseminated untrue and misleading statements to damage SMIC’s reputation and goodwill.
TSMC “rather than competing fairly in the marketplace, have undertaken a concerted effort to infringe SMIC’s legal rights unfairly,”
TSMC filed in California for a reason, California has significant case law in regards to protecting intellectual property. SMIC filed in Bejing for a reason, China has scant case law in regards to intellectual property. It will be interesting how the Bejing and the California court proceedings compare. The California trial, which began this month, is expected to last 50-60 days, and is being broadcast by the Courtroom View Network. Trial updates will be available via my Twitter: DanielNenni
Sun Microsystems Autopsy Part II: Death by Six Sigma
As the story goes, Scott McNealy played golf with Jack Welch one afternoon and came home with a bad case of “across the board Six Sigma”. I first learned of Six Sigma from a friend who is a Black Belt. An afternoon at Hooters, a couple of pitchers of beer later, I knew everything I would ever want to know about the latest trend in business management strategy.
My first reaction was laughter (on the inside), this incredibly out of shape guy being a black belt at anything. My guess is that martial arts practitioners around the world popped a vein at the concept of having a black belt in bureaucracy. My second reaction was deja vu TQM from my grad school days with W. Edwards Demming and the rebuilding of Japan after WWII. Read his book “Out of the Crisis” and you will see why I changed my focus to cross cultural relations, but I digress.
At the time, Sun was feeling the pain of the Dot Com Bubble, in dire need of better processes, making them a perfect candidate for the latest buzzword that would give shareholders false hope. Sun Sigma sounded like a great idea, it was successful at Ford and GE, right? Well Sun was no Ford or GE. Every Sun group, Director on down, had a black belted person with a ton of influence. If you liked windsock meetings, you were a perfect candidate to be a black belt. Almost every substantial project had either a Sun Shot (one day Sigma meeting) or was a full fledged Sun Sigma project. Black belt led projects seemed to lose all fun and spontaneity, bottom line, it added value a small percentage of the time, the rest of the time it was unnecessary weight. If you want to slow innovation (and execution) to a crawl, apply the Six Sigma methodology across the board, works every time.
Take a look at the list of companies on the Six Sigma Wikipedia page, no IBM, H-P, Apple, or Intel, all innovation driven companies, all industry leaders. The list is of companies that claim to have successfully implemented Six Sigma in some form or another, so no Sun Microsystems either.

Of course there are two sides to every story. People defend Six Sigma by pointing out implementation is everything, so without knowing how it was implemented you cannot judge success versus failure. Great argument, works on just about everything, “you just didn’t try hard enough”, I use it on my children all the time.
While there are many similarities, the basic difference between TQM and Six Sigma is the approach. While TQM is process centric, Six Sigma focuses on improving quality by reducing the number of defects. The end result however, total quality of results, will be about the same. My preferred business management strategy is a focus on job descriptions with an executive dictum of “If you want to get paid, do your job!” Any questions?
TSMC Restrictive Design Rules and 32/28nm Yield
To follow up one of my most viewed blogs: TSMC 40nm Yield Explained, let’s talk about Restrictive Design Rules (RDRs) and 32/28nm yield. RDRs have been seriously discussed since 65nm, by restricting the freedom layout designers enjoy today a foundry can better guarantee the manufacturability of a semiconductor design. RDRs even have a Wikipedia page.

The #46DAC Advanced Node Panel: Making the Case for Restricted Design Rules was stacked with semiconductor experience: Norma Rodriguez, senior member of technical staff at AMD, Tom Quan, senior director of EDA and design service marketing at TSMC, and Arjun Rajagopal, member of technical staff at TI’s DSP group.
Digital 32/28nm designs are less complicated. According to Tom Quan, design and modeling infrastructure for 32/28 nm is ready at TSMC, it includes statistical Spice models, a reference flow, and RDR-based standard cells with regular layout patterns. Arjun Rajagopal admitted that RDRs will increase area, but will help with process variability and predictability. Norma Rodriguez spoke in detail about 22nm RDRs but my feeling is that it was AMD microprocessor centric, which is quite different than GP or LP foundry processes.
I agree with Tom Quan, digital designs will be less of a problem with RDRs, but analog and mixed signal designs are another challenge all together. At 45nm and below, proximity variation effects (channel stress, contact spacing, poly-to-poly spacing, STI spacing, well spacing, and OD-to-OD spacing) are a major disturbance.

It’s a catch-22 really, you don’t know the actual effects until layout, but will have to iterate back to the schematic to adjust for them, creating a time consuming iterative loop. The unfortunate reality is that probably only 10% of the instances in an analog mixed/signal design will have proximity problems so guard banding 100% of the devices will be costly.
Let’s talk about the analog design flow to highlight how these proximity effects could fundamentally alter a circuit designers job. In my experience, the designer creates a schematic and uses foundry-provided spice models to run simulations to determine performance under nominal process conditions. At 32/28nm, the designer is aware that various proximity and stress effects will significantly impact circuit behavior. What does this do to the rest of the design flow? The designer needs to simulate over various process/environmental corners, simulate for local mismatch issues to determine yield robustness. All these tasks are typically done during the circuit design stage. But now, with all these proximity effects, should the designer hold off until after layout? Does the designer just assume that the layout engineer will be ultra-conservative using RDR’s (if available), heuristics, or guess-work to guard-band during layout? How about giving the designer visibility/inputs into the layout stage? If the designer could determine which devices are more or less sensitive to proximity effects and be able to provide this information to the layout engineer, it would significantly decrease yield risk during the front end design task at 45nm and below nodes.

The only functional proximity solver that I’m aware of today is from Solido Design. I have been helping Solido with Strategic Foundry Relationships so I know this by experience. For more information, read what Ron Wilson from EDN had to say: Solido adds well-proximity estimation to Variation Designer, or check out the Solido Proximity Package Data Sheet. Proximity variation effects are a serious problem for analog and mixed signal designs at 32/28nm, believe it.
Sun Microsystems Autopsy: Death by Reverse Darwinism
Founded in 1982, Sun Microsystems, a landmark in Silicon Valley, originated the UNIX workstation market with the mantra “The network is the computer”. The Sun wikipedia page is a good place to start, next try High Noon: The Inside Story of Scott McNealy and the Rise of Sun Microsystems by Karen Southwick, the Oracle acquisition is where it will finish.
After missing several opportunities to work for Sun in the early days, I settled for a job with Solbourne Computer, the first of a few Sun compatible companies. Solbourne made the first multiprocessor version of Sun servers and did quite well as a result. I paid cash for my first house, thank you Solbourne Computer. In return for expanding the Sun market share, Sun made it virtually impossible for Solbourne (meaning born of sun) to succeed. Strangely enough Solbourne ended up becoming a successful Oracle systems integrator, but I digress.
The Sun corporate culture was set by the executive staff, hiring the top talent Silicon Valley had to offer. Sun CEO Scott McNealy set the maverick standard with the often repeated “To ask permission is to seek denial” dictum. Scott even named one of his sons Maverick! The best and brightest were hired, were promoted, innovation was king. The likes of Andy Bechtolsheim, Bill Joy, John Gilmore, Whitfield Diffie, Radia Perlman, Marc Tremblay, Ned Freed, John Gage, James Gosling, Jon Bosak, went through Sun’s revolving doors, some more than once. Insiders say Jonathan I. Schwartz was once one of those, but now that he strapped on a $12M+ golden parachute the only time you see him walking around SUN is with two armed body guards.

Unfortunately when the dot.com bubble burst so did Sun. From my experience working with Sun I would call it death by Reverse Darwinism or the rise of mediocrity. Sun middle management is bloated with people that are good in meetings, intelligent people that talk a good game, but are as maverick as Sarah Palin, and accomplish about as much. Analysys Paralysis runs rampant, these people are simply windsocks going wherever the prevailing breeze takes them. Reverse Darwinism is a fatal disease for technology dependent companies. Any time you see a company fly so high, accomplish so much, only to flat line, the cause of death is most always reverse darwinism, believe it.

Oracle is quite the opposite, more of an autocracy, run not so much by founder Larry Ellison, but by President Charles E. Phillips, Jr. and President and CFO Safra A. Catz, who translate Larry’s visions into revenues. One of Fortunes 50 most powerful women, also known as the Oracle Enforcer, Safra Catz will be the ultimate defibrillator for the mediocrity rank and file that brought Sun to its knees. Expect a literal blood bath, more pink slips than Victoria’s Secret, thousands more on the global dole.
Even more shocking is that the DOJ approved the acquisition and the rubber stamping EU did NOT! The sticking point is MySQL (as mentioned in my previous blog) which accounts for an insignificant $300M of the more than $19B database market. Think of who the winners are in this acquisition: certainly Oracle and Sun, and the soon to be combined customer base. The losers: IBM and HP. Now ask yourself who is really behind the EU delay?
























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